The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Jul. 20, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Te-Yang Lai, Hsinchu, TW;

Yen-Fu Chen, Taipei, TW;

Shu-Han Chen, Hsinchu City, TW;

Tsung-Da Lin, Hsinchu, TW;

Da-Yuan Lee, Hsinchu County, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

Semiconductor structures and methods are provided. An example method includes receiving a workpiece that includes a substrate, first channel members over a first region of the substrate, second channel members over a second region of the substrate, and third channel members over a third region of the substrate, depositing a first gate dielectric layer to wrap around each of the first channel members, each of the second channel members, and each of the third channel members, selectively depositing a first dipole layer to wrap around each of the third channel members, performing a first anneal process to drive a first dopant in the first dipole layer into the first gate dielectric layer around the third channel members, removing the first dipole layer, and after the removing, depositing a second gate dielectric layer to wrap around the first channel members, the second channel members, and the third channel members.


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