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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12717999 B1

PDFFull Text
Date of Patent:
Aug. 25, 2026

Filed:

Jun. 20, 2023

Dynamic ordering of design rule checks

Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Chin-Hsiung Hsu, Taipei, TW;

Sheng-Wei Yang, Hsinchu, TW;

Chau-Chin Huang, Hsinchu, TW;

Yu-Hsiang Cheng, Hsinchu, TW;

Guo-Ting Wang, Hsinchu, TW;

James Yu, Taipei, TW;

Philip Hui-Yuh Tai, Cupertino, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:

WOMBLE BOND DICKINSON (US) LLP

Primary Examiner:

Phallaka Kik

Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/27 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06N 3/0464 (2023.01); G06N 3/08 (2023.01); G06N 7/06 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/27 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06N 3/0464 (2023.01); G06N 3/08 (2013.01); G06N 7/06 (2013.01); G06N 20/00 (2019.01);
Abstract

A method includes: receiving an integrated circuit design including a plurality of cells; performing a first plurality of design rule checks on a first portion of the plurality of cells of the integrated circuit design based on a sequence of design rule checkers arranged in a first order; collecting data on an execution of the design rule checkers on the first portion of the plurality of cells; updating, by a processing device, the sequence of design rule checkers, based on the data, to a second order of design rule checkers; and performing a second plurality of design rule checks on a second portion of the plurality of cells of the integrated circuit design based on the sequence of design rule checkers arranged in the second order.

Find Patent Forward Citations

Hsu, Chin-Hsiung. (2026). Dynamic ordering of design rule checks (U.S. Patent No. 12717999). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12717999

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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