The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2026
Filed:
Apr. 21, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/29 (2006.01); H01L 23/538 (2006.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 74/10 (2026.01); H10W 74/43 (2026.01); H10W 76/05 (2026.01); H10W 74/40 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 74/147 (2026.01); H10W 70/093 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 74/141 (2026.01); H10W 74/43 (2026.01); H10W 76/05 (2026.01); H10W 74/40 (2026.01); H10W 90/724 (2026.01);
Abstract
A method of forming an IC structure includes bonding a first die to a first side of a substrate and bonding a second die to the first side of the substrate. The second die is adjacent to the first die and a gap is defined between the first and second dies. The method includes forming a first dielectric layer (DL) over the first and second dies and in the gap, forming a first opening in the first DL in the gap, forming a second DL over the first DL and in the first opening. The first DL includes a higher film stress in absolute value than the second DL.