The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2026
Filed:
Oct. 27, 2023
Infineon Technologies Canada Inc., Ottawa, CA;
Mihalis Michael, San Jose, CA (US);
Farzin Najafi, Ottawa, CA;
Mohammad Shafayet Zamil, Nepean, CA;
Abhinandan Hemant Dixit, Kanata, CA;
Infineon Technologies Canada Inc., Ottawa, CA;
Abstract
A package for an integrated circuit die (e.g., a chip). A routing layer is layered between the chip and package contacts of the package. The chip has a planar surface along which the chip includes die contacts. The routing layer lies along the planar surface of the chip, and electrically connects the die contacts of the chip to the package contacts of the package. This allows the chip, the routing layer, and the package contacts to be stacked together to form a relatively thin, compact package. The routing layer connects the die contacts of the chip to the package contacts of the package, such that the die contacts need not have the same layout as the package contacts, thus allowing packages with the same package contact layouts to be used to package chips with varying die contact layouts. A lead in conductive contact with the package contact.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile