The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2026
Filed:
Jun. 04, 2021
Intel Corporation, Santa Clara, CA (US);
Leonard P. Guler, Hillsboro, OR (US);
Tahir Ghani, Portland, OR (US);
Charles H. Wallace, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures. A plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of a plurality of gate structures and co-planar with an uppermost surface of a plurality of conductive trench contact structures. A dielectric layer is over the plurality of gate structures, over the plurality of conductive trench contact structures, and over the plurality of dielectric spacers. The dielectric layer has a planar uppermost surface. An opening is in the dielectric layer, the opening exposing one of the plurality of gate structures or one of the plurality of conductive trench contact structures. A conductive via is in the opening. The conductive via has an uppermost surface co-planar with the planar uppermost surface of the dielectric layer.