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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12707681 B1

PDFFull Text
Date of Patent:
Aug. 11, 2026

Filed:

Feb. 16, 2022

Multigate transistors with capping layers and a buffer layer comprising germanium

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shahaji B. More, Hsinchu City, TW;

Cheng-Han Lee, New Taipei City, TW;

Shih-Chieh Chang, Taipei City, TW;

Wan-Hsuan Hsieh, Hsinchu City, TW;

Chung-En Tsai, Hsinchu County, TW;

Chee-Wee Liu, Taipei City, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

Wael M Fahmy

Assistant Examiner:

Aneesa Riaz Baig

Int. Cl.
CPC ...
H01L 23/498 (2006.01); G11C 5/06 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/85 (2025.01); H10D 64/01 (2025.01); H10D 64/64 (2025.01); H10H 20/852 (2025.01); H10H 20/857 (2025.01); H10P 14/20 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6757 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10P 14/3411 (2026.01); H10P 14/3412 (2026.01); H10P 14/3452 (2026.01);
Abstract

The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.

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