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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12707634 B1

PDFFull Text
Date of Patent:
Aug. 11, 2026

Filed:

Oct. 19, 2021

Three-dimensional integration structure and method of forming the same

Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventor:

Siping Hu, Wuhan, CN;

Assignee:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Marcos D Pizarro

Int. Cl.
CPC ...
H10B 41/35 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); H10B 80/00 (2026.01); H10W 20/20 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H10B 80/00 (2023.02); H10W 20/20 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/20 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/726 (2026.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a first substrate layer having a first side over which devices are formed. In the semiconductor device, a first dielectric structure is formed over the first side of the first substrate layer in which the devices are positioned. The first dielectric structure includes a bottom surface in contact with the first side of the first substrate layer. A portion of the bottom surface of the first dielectric structure is not covered by the first substrate layer. The semiconductor device also includes a first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned at a same side of the bottom surface of the first dielectric structure. The first electronic structure is bonded to the first dielectric structure.

Find Patent Forward Citations

Hu, Siping. (2026). Three-dimensional integration structure and method of forming the same (U.S. Patent No. 12707634). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12707634

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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