The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 06, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ta-Chun Lin, Hsinchu, TW;

Kuo-Hua Pan, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 14/20 (2026.01); H10P 50/00 (2026.01); H10P 50/64 (2026.01);
U.S. Cl.
CPC ...
H10B 10/125 (2023.02); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0179 (2025.01); H10D 84/0184 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01); H10P 14/3411 (2026.01); H10P 14/3462 (2026.01); H10P 50/642 (2026.01); H10P 50/691 (2026.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device comprises a first channel structure. The semiconductor device structure includes a first gate stack wrapped around the first channel structure, and a second device formed over the first device. The second device comprises a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure include a second gate stack wrapped around the second nanostructures, and a portion of the first gate stack is higher than a topmost second nanostructure.


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