The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2026

Filed:

Jun. 02, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seyun Kim, Suwon-si, KR;

Kyunghun Kim, Suwon-si, KR;

Sunho Kim, Suwon-si, KR;

Hyungyung Kim, Suwon-si, KR;

Seungyeul Yang, Suwon-si, KR;

Gukhyon Yon, Suwon-si, KR;

Minhyun Lee, Suwon-si, KR;

Joonsuk Lee, Suwon-si, KR;

Seokhoon Choi, Suwon-si, KR;

Hoseok Heo, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/35 (2023.01); G11C 16/04 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10D 62/80 (2025.01); H10D 62/84 (2025.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 62/84 (2025.01); H10D 62/882 (2025.01);
Abstract

Provided is a nonvolatile memory device. The nonvolatile memory device includes: a channel layer; a plurality of gate electrodes and a plurality of insulating layers being spaced apart from the channel layer and being alternately arranged; a charge trap layer between the channel layer and a gate electrode, and a charge tunneling layer between the channel layer and the charge trap layer.


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