The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Mar. 14, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;

Inventors:

Wei-Hao Chen, New Taipei, TW;

Li-Hsien Huang, Zhubei, TW;

Syufong Li, Taoyuan, TW;

Yao-Chun Chuang, Hsinchu, TW;

Yinlung Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 74/10 (2026.01); H10W 72/20 (2026.01); H10W 72/00 (2026.01); H10W 74/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 74/117 (2026.01); H10W 72/20 (2026.01); H10W 72/884 (2026.01); H10W 74/00 (2026.01); H10W 90/756 (2026.01);
Abstract

A method of fabricating a semiconductor device that includes a first die component and at least one second die component. The first die component includes a substrate, a dielectric layer on the substrate, and one or more metal pads positioned on the dielectric layer. The first die component further includes a passivation/bond film layer that is formed over the one or more metal pads, and one or more bond pad vias that extend through the passivation/bond film layer and contact one or more metal pads. The at least one second die component is bonded to the first die component and includes a substrate, and one or more through silicon vias, with the one or more through silicon vias contacting the one or more bond pad vias.


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