The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jun. 17, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Chiang Tsai, Hsinchu City, TW;

Fu-Hsiang Su, Zhubei City, TW;

Ke-Jing Yu, Kaohsiung City, TW;

Jyh-Huei Chen, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/46 (2026.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/66 (2025.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10W 20/46 (2026.01); H10D 30/024 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/258 (2025.01); H10D 64/679 (2025.01); H10W 20/072 (2026.01); H10W 20/076 (2026.01); H10W 20/081 (2026.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a first insulating capping feature formed over the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed adjacent to the gate electrode layer and a second insulating capping feature formed over the source/drain contact structure. The second insulating capping feature and the first insulating capping feature are made of different materials, and an air gap directly below and in direct contact with the second insulating capping feature.


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