The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Oct. 26, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuo-Cheng Ching, Hsinchu County, TW;

Ying-Keung Leung, Hsinchu City, TW;

Chi On Chui, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 14/60 (2026.01); H10P 14/61 (2026.01); H10P 14/694 (2026.01); H10P 95/00 (2026.01);
U.S. Cl.
CPC ...
H10D 84/834 (2025.01); H10D 62/115 (2025.01); H10D 64/017 (2025.01); H10D 64/513 (2025.01); H10D 84/0144 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10P 14/61 (2026.01); H10P 14/6339 (2026.01); H10P 14/6682 (2026.01); H10P 14/6687 (2026.01); H10P 14/69433 (2026.01); H10P 95/00 (2026.01); H10D 84/0142 (2025.01);
Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.


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