The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Apr. 12, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Tsung-Hua Yang, Tainan City, TW;

Cheng-Bo Shu, Tainan City, TW;

Chia-Ta Hsieh, Tainan, TW;

Ping-Cheng Li, Kaohsiung City, TW;

PO-Wei Liu, Tainan City, TW;

Shih-Jung Tu, Tainan City, TW;

Tsung-Yu Yang, Tainan City, TW;

Yun-Chi Wu, Tainan City, TW;

Yu-Wen Tseng, Chiayi City, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10P 30/20 (2026.01); H10P 30/22 (2026.01);
U.S. Cl.
CPC ...
H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/116 (2025.01); H10D 62/393 (2025.01); H10P 30/204 (2026.01); H10P 30/21 (2026.01); H10P 30/22 (2026.01);
Abstract

An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.


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