The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Apr. 19, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hung-Chang Chang, Tainan City, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Eugene Chen, Taipei City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/8503 (2025.01);
Abstract

Some implementations herein describe a carrier structure and techniques of forming a semiconductor device using the carrier structure. The carrier structure includes a core layer formed from a layer of a high bandgap material, a backside layer stack formed on a backside surface of the layer of the high bandgap material, and a frontside layer stack formed on a frontside surface of the layer of the high bandgap material. The backside layer stack includes a backside chucking layer (e.g., a layer of a polysilicon material) that intervenes between a backside diffusion barrier layer and a backside adhesion layer. The frontside layer stack includes a corresponding frontside diffusion barrier layer that interfaces directly with a corresponding frontside adhesion layer. A corresponding frontside chucking layer has been eliminated. By eliminating the frontside chucking layer, a likelihood of thermally-induced stresses and/or strains due to a coefficient of thermal expansion mismatch between layers of the frontside layer stack and other layers of the semiconductor device, during formation of the semiconductor device, is reduced.


Find Patent Forward Citations

Loading…