Memory device, system, and operating method for facilitating programming verification operations

Abstract

The present disclosure provides memory devices, operating methods, memory systems. An example memory device includes a memory array and a peripheral circuit. The memory array includes a first and a second finger memory region, each region including multiple memory cell strings. Each memory cell string includes a first bottom select transistor (BSG). First BSGs in the first and second finger memory regions have a first and a second threshold voltage, respectively. The peripheral circuit is configured to: apply a first bias voltage to the BSGs in the first pre-charge phase of a programming verification operation on the first finger memory region; apply a second bias voltage to the first BSGs after the first pre-charge phase; the first bias voltage is smaller than the second bias voltage; and the second bias voltage is smaller than the second threshold voltage and greater than the first threshold voltage.