The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

May. 24, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yi-Fan Chen, New Taipei City, TW;

Sen-Hong Syue, Hsinchu County, TW;

Huicheng Chang, Tainan City, TW;

Yee-Chia Yeo, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 84/01 (2025.01); H10P 34/42 (2026.01); H10P 72/00 (2026.01); H10P 72/76 (2026.01); H10P 74/00 (2026.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0191 (2025.01); H10D 84/0193 (2025.01); H10P 34/422 (2026.01); H10P 72/0436 (2026.01); H10P 72/0602 (2026.01); H10P 72/7618 (2026.01); H10P 74/23 (2026.01);
Abstract

A method of fabricating an integrated circuit (IC) is provided. The method includes the following steps: providing a substrate; forming a p-well region in the substrate; forming an n-well region in the substrate; conducting a microwave annealing at a first temperature; conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature; and fabricating a plurality of field-effect transistors (FETs) in the p-well region and the n-well region.


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