The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2026
Filed:
May. 12, 2023
Applicant:
Kioxia Corporation, Minato-ku, JP;
Inventors:
Assignee:
KIOXIA CORPORATION, Tokyo, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/06 (2006.01); H01L 29/788 (2006.01); H10D 30/69 (2025.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10D 30/711 (2025.01); H10W 74/117 (2026.01);
Abstract
The semiconductor wiring has the N-well layer of the impurity layer in the P substrate formed in the region where the poly wiring and P substrate face each other, wherein the N-well layer is electrically floating, is not used as a circuit element, and does not input or output signals. The semiconductor wiring is used as a transmission path of a high voltage signal, and used for a wiring that transmits a write signal of information at the memory cell array of the semiconductor memory device.
Sueyama, Takao. (2026). Booster circuit for semiconductor memory device (U.S. Patent No. 12696493). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12696493
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile