The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Aug. 15, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Si-Woo Lee, Boise, ID (US);

Scott E. Sills, Boise, ID (US);

David K. Hwang, Boise, ID (US);

Yoshitaka Nakamura, Boise, ID (US);

Yuanzhi MA, Boise, ID (US);

Glen H. Walters, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/05 (2023.02); H10B 12/03 (2023.02); H10B 12/30 (2023.02); H10B 12/482 (2023.02);
Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.


Find Patent Forward Citations

Loading…