Parameterized cell with multiple layout configuration options

Abstract

Disclosed are a process design kit (PDK) product and also a design system and a design method that employ the PDK product to layout IC designs including 3D IC designs. The PDK product includes a storage medium and a PDK, including a library of cells, stored thereon. The cells can include parameterized cells (pcells) representing various IC components. The pcells are parameter-customizable and one or more of the pcells are also layout configuration-customizable. Each parameter and layout configuration-customizable pcell includes customization script, which is executable by a processor in response to inputs specific to that pcell and which can cause the processor to place an instance of that pcell with customized parameters in a 3D IC layout according to a selected layout configuration option (e.g., a single-chip layout configuration option or a multi-chip layout configuration option).