The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2026

Filed:

Apr. 15, 2022
Applicant:

Ansys, Inc., Canonsburg, PA (US);

Inventors:

David Geb, Walnut Creek, CA (US);

Saeed Asgari, Westborough, MA (US);

Akhilesh Kumar, Milpitas, CA (US);

Jimin Wen, Pleasanton, CA (US);

Norman Chang, Fremont, CA (US);

Hsiming Pan, San Jose, CA (US);

Mehdi Abarham, Belmont, CA (US);

Haiyang He, Washington, PA (US);

Viralkumar Girishchandra Gandhi, Nashua, NH (US);

Assignee:

ANSYS, INC., Canonsburg, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/28 (2020.01); G06F 30/373 (2020.01); G06F 113/18 (2020.01); G06F 119/08 (2020.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/28 (2020.01); G06F 30/373 (2020.01); G06F 2113/18 (2020.01); G06F 2119/08 (2020.01);
Abstract

In one embodiment, several reduced order models (ROMs), each at a different scale, are developed to create a multiscale ROM for a given system, which can include one or more integrated circuits (ICs), for simulating thermal responses (e.g., heating in the ICs and the system) as a result of usage scenarios of the IC and system (in which power is applied on the IC and in the system) over time. An IC, package and system can be thermally characterized to determine transient temperature response to a power source in each IC; this characterization can use simulations of the power source to simulate temperature responses at points in the IC, package and system, and these responses provide a set of thermal training data. An algorithm generates a linear time-invariant (LTI) state-space thermal macromodel or ROM at each of the different scales on-chip and in system, from the set of thermal step response training data, and combines them into a multiscale ROM, which can be distributed and solved on many CPUs. When the multiscale ROM is used, power accounting can be used across the scales to conserve power. On IC symmetry and inverse heat transfer properties can be used to reduce the amount of thermal characterization operations.


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