The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Apr. 06, 2023
Applicants:

Nexperia Technology (Shanghai) Ltd., Shanghai, CN;

Nexperia B.v., Nijmegen, NL;

Inventors:

Wei Gong, Shanghai, CN;

Chunlin Zhu, Shanghai, CN;

Ke Jiang, Shanghai, CN;

Assignees:

Nexperia Technology (Shanghai) Ltd., Shanghai, CN;

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 72/90 (2026.01); H10W 40/00 (2026.01); H10W 70/65 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/50 (2026.01); H10W 72/60 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 40/00 (2026.01); H10W 70/65 (2026.01); H10W 90/701 (2026.01); H10W 72/5475 (2026.01); H10W 72/631 (2026.01); H10W 72/652 (2026.01); H10W 72/871 (2026.01); H10W 72/926 (2026.01); H10W 72/944 (2026.01); H10W 90/754 (2026.01); H10W 90/763 (2026.01);
Abstract

A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.


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