The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Feb. 24, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Choongbin Yim, Suwon-si, KR;

Hyonchol Kim, Suwon-si, KR;

Sungbum Kim, Suwon-si, KR;

Gitae Park, Suwon-si, KR;

Jiyong Park, Suwon-si, KR;

Jinwoo Park, Suwon-si, KR;

Jongbo Shim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 42/00 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 72/00 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 42/121 (2026.01); H10W 70/685 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 70/093 (2026.01); H10W 72/07236 (2026.01); H10W 90/24 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/752 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package includes: a package substrate including a redistribution layer, a lower protective layer, and a plurality of support protrusions, wherein the redistribution layer has first and second pads disposed on the package substrate, wherein the lower protective layer has first openings and a trench, wherein the trench exposes the second pads, and wherein the plurality of support protrusions are disposed in the trench; a semiconductor chip disposed on the package substrate and including connection pads electrically connected to the redistribution layer; an encapsulant disposed on at least a portion of the semiconductor chip; first connection bumps electrically connected to the first pads, respectively; a passive device disposed in the trench of the lower protective layer and electrically connected to the second pads; and a sealant covering at least a portion of the passive device and extending into the trench.


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