The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Jul. 03, 2023
Applicant:

Celestial Ai Inc., Santa Clara, CA (US);

Inventors:

Ankur Aggarwal, Pleasanton, CA (US);

Jeremy Matthew Plunkett, San Jose, CA (US);

Assignee:

Celestial AI Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H10W 20/20 (2026.01); H10W 70/63 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); H10W 70/635 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/652 (2026.01); H10W 72/242 (2026.01); H10W 72/244 (2026.01); H10W 72/252 (2026.01); H10W 72/922 (2026.01); H10W 72/9223 (2026.01); H10W 72/923 (2026.01); H10W 72/934 (2026.01); H10W 72/942 (2026.01); H10W 72/952 (2026.01);
Abstract

One embodiment is a method including forming a partial through-substrate via (TSV) plug in a front side of a wafer, the partial TSV plug having a front side, a back side, and a body with a variable dimension in the body so that a largest dimension is at the back side of partial TSV plug. A cavity is etched in a back side of the wafer that exposes the back side of the partial TSV plug and a portion of a front side interconnect in a common etched cavity. A conductive material is deposited to connect the exposed portion of the front side interconnect to the back side of the wafer and to connect the exposed back side of the partial TSV plug to the back side of the wafer without connecting the partial TSV plug and the portion of the front side interconnect.


Find Patent Forward Citations

Aggarwal, Ankur. (2026). Via formed in a wafer using a front-side and a back-side process (U.S. Patent No. 12690438). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12690438

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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