The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Dec. 05, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Juntao Li, Cohoes, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Jingyun Zhang, Albany, NY (US);

Kisik Choi, Watervliet, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor structure with matched frontside and backside source/drain contact areas is provided. The semiconductor structure includes a backside contact region, a first source/drain region disposed on the backside contact region, wherein a shared surface between the backside contact region and a backside of the first source/drain region forms a first contact area, inner spacers disposed on opposite sides of the first source/drain region, wherein the inner spacers control a size of first contact area, and a frontside interlayer dielectric disposed on the first source/drain region, wherein a shared surface between the frontside interlayer dielectric and a frontside of the first source/drain region forms a second contact area, wherein the size of the first contact area matches a size of the second contact area.


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