The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2026
Filed:
Dec. 24, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
Shakul Tandon, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03F 9/00 (2006.01); G03F 1/42 (2012.01); G03F 1/84 (2012.01); G03F 7/00 (2006.01); G06T 7/00 (2017.01); G06T 7/66 (2017.01); G06T 7/73 (2017.01); H01J 37/22 (2006.01); H10W 46/00 (2026.01);
U.S. Cl.
CPC ...
G03F 9/7076 (2013.01); G03F 1/42 (2013.01); G03F 1/84 (2013.01); G03F 7/70633 (2013.01); G03F 7/70683 (2013.01); G03F 9/7046 (2013.01); G06T 7/0004 (2013.01); G06T 7/66 (2017.01); G06T 7/73 (2017.01); H01J 37/222 (2013.01); H10W 46/00 (2026.01); G06T 2207/30148 (2013.01); H10W 46/301 (2026.01); H10W 46/401 (2026.01);
Abstract
Embodiments described herein may be related to apparatuses, processes, and techniques related to using full stack overlay cell (FSOL) targets within lithography masks and on fabricated layers of a substrate in order to align or to assess the alignment of fabricated layers of the substrate during the substrate manufacturing process. Other embodiments may be described and/or claimed.