The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Jun. 01, 2023
Applicant:

Siliconware Precision Industries Co., Ltd., Taichung City, TW;

Inventors:

Fang-Lin Tsai, Taichung City, TW;

Wei-Son Tsai, Taichung City, TW;

Kun-Yuan Luo, Taichung City, TW;

Pei-Geng Weng, Taichung City, TW;

Sheng-Hua Yang, Taichung City, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 74/10 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 70/652 (2026.01); H10W 72/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 74/121 (2026.01); H10W 74/117 (2026.01); H10W 70/09 (2026.01); H10W 70/60 (2026.01); H10W 70/6528 (2026.01); H10W 72/07307 (2026.01); H10W 90/736 (2026.01);
Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element is pasted on a routing layer that is configured with a plurality of conductive pillars, then the electronic element, the conductive pillars and the routing layer are covered with a cladding layer, and a circuit structure electrically connected to the electronic element and the conductive pillars is formed on the cladding layer. Therefore, the conductive pillars can be directly formed on the routing layer and the dielectric layer is omitted, so there is no need to consider the thickness of the dielectric layer, so as to facilitate the thinning of the electronic package.


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