The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Mar. 20, 2024
Applicants:

Global Unichip Corporation, Hsinchu City, TW;

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Liang-Kai Chen, Hsinchu City, TW;

Chih-Chiang Hung, Hsinchu City, TW;

Wen-Yi Jian, Hsinchu City, TW;

Yuan-Hung Lin, Hsinchu City, TW;

Sheng-Fan Yang, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10W 90/724 (2026.01);
Abstract

A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.


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