The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Sep. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jeremy Ecton, Gilbert, AZ (US);

Brandon Marin, Gilbert, AZ (US);

Srinivas Pietambaram, Chandler, AZ (US);

Hiroki Tanaka, Gilbert, AZ (US);

Suddhasattwa Nad, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/68 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/614 (2026.01); H10W 70/68 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 70/60 (2026.01); H10W 70/682 (2026.01); H10W 90/728 (2026.01); H10W 90/798 (2026.01);
Abstract

Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.


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