The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Oct. 19, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Tsung-Sheng Kang, Ballston Lake, NY (US);

Tao Li, Slingerlands, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Oleg Gluschenkov, Tannersville, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 86/60 (2025.01); H10D 86/01 (2026.01); H10D 86/40 (2025.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); H10D 86/0214 (2025.01); H10D 86/0221 (2025.01); H10D 86/421 (2025.01); H10D 86/441 (2025.01);
Abstract

A semiconductor structure comprises at least one first nanosheet transistor and at least one second nanosheet transistor disposed on a dielectric layer. The first nanosheet transistor comprises at least one first source/drain region disposed on a side of the first nanosheet transistor. The second nanosheet transistor comprises at least one second source/drain region disposed on a side of the second nanosheet transistor. The second source/drain region has a larger dimension along a given direction than a dimension of the first source/drain region along the given direction. One of a dielectric fill layer and an air gap is disposed in the dielectric layer and under the second source/drain region. A semiconductor layer is disposed under the second source/drain region, in the dielectric layer and around the one of the dielectric fill layer and the air gap.


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