The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Sep. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Michelle C. Jen, Mountain View, CA (US);

David J. Harriman, Portland, OR (US);

Zuoguo Wu, San Jose, CA (US);

Debendra Das Sharma, Saratoga, CA (US);

Noam Dolev Geldbard, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3234 (2019.01); G06F 1/3225 (2019.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/3225 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); Y02D 10/00 (2018.01);
Abstract

A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.


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