The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Dec. 14, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Nicholas Alexander Polomoff, Hopewell Junction, NY (US);

Huai Huang, Clifton Park, NY (US);

Ravi K. Bonam, Albany, NY (US);

Haojun Zhang, Schenectady, NY (US);

Katsuyuki Sakuma, Fishkill, NY (US);

Mukta Ghate Farooq, Hopewell Jct, NY (US);

Eric Perfecto, Poughkeepsie, NY (US);

Spyridon Skordas, Troy, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 74/00 (2026.01); H10P 50/00 (2026.01); H10W 72/00 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10P 74/232 (2026.01); H10P 50/691 (2026.01); H10W 74/016 (2026.01); H10W 74/121 (2026.01); H10W 90/00 (2026.01); H10W 72/019 (2026.01); H10W 72/0198 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 90/724 (2026.01); H10W 90/792 (2026.01); H10W 90/794 (2026.01);
Abstract

A first semiconductor build has a first back end of the line having a dielectric stack, metal wiring lines, vias and joining pads that are constructed into a first electrical connected path, having a first and second end, and passing through a portion of the first back end of the line dielectric stack. A second semiconductor build has a similar first electrical connected path. The first and second builds are bonded to a third semiconductor build, with the second end of the first electrical connected path of the first semiconductor build and the first end of the first electrical connected path of the second semiconductor build electrically coupled together in series via a first electrical connected path of the third semiconductor build, such that the resistance/conductivity measured from the first end of the first semiconductor build to the second end of the second semiconductor build verifies conductivity of the paths.


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