The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Apr. 17, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Chih-Yu Chang, New Taipei City, TW;

Han-Jong Chia, Hsinchu, TW;

Sai-Hooi Yeong, Zhubei City, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10B 43/20 (2023.01); H10D 8/00 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/80 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 88/00 (2025.01); H10D 99/00 (2025.01); H10N 70/00 (2023.01); H10P 14/20 (2026.01); H10B 43/35 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/84 (2023.02); H10B 43/20 (2023.02); H10B 63/20 (2023.02); H10B 63/30 (2023.02); H10D 8/00 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/80 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01); H10D 99/00 (2025.01); H10N 70/011 (2023.02); H10P 14/3434 (2026.01); H10B 43/35 (2023.02); H10N 70/20 (2023.02);
Abstract

Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.


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