The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Oct. 24, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Cheng Hung Lee, Hsinchu, TW;

Chien-Yu Huang, Hsinchu, TW;

Chia-En Huang, Hsinchu, TW;

Yen-Chi Chou, Hsinchu, TW;

Shao Hsuan Hsu, Hsinchu, TW;

Tzu-Chun Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 5/06 (2006.01); G11C 11/418 (2006.01); H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/85 (2025.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
G11C 11/418 (2013.01); G11C 5/063 (2013.01); H10B 10/12 (2023.02); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 84/853 (2025.01); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract

A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.


Find Patent Forward Citations

Lee, Cheng. (2026). Memory device (U.S. Patent No. 12676186). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12676186

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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