The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Sep. 23, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Joan Rey Villarba Buot, Escondido, CA (US);

Hong Bok We, San Diego, CA (US);

Michelle Yejin Kim, Carlsbad, CA (US);

Aniket Patil, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 70/69 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/685 (2026.01); H10W 70/05 (2026.01); H10W 70/095 (2026.01); H10W 70/65 (2026.01); H10W 70/69 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 90/724 (2026.01);
Abstract

A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer.


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