The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2026
Filed:
Aug. 31, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jeremy D. Ecton, Gilbert, AZ (US);
Hiroki Tanaka, Gilbert, AZ (US);
Brandon Christian Marin, Gilbert, AZ (US);
Srinivas V. Pietambaram, Chandler, AZ (US);
Suddhasattwa Nad, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/68 (2006.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/05 (2026.01); H10W 70/093 (2026.01); H10W 70/095 (2026.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 70/692 (2026.01); H10W 90/00 (2026.01); H10W 90/401 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract
A glass core with a cavity-less local interconnect component architecture for complex multi-die packages. The apparatus has the local interconnect component attached directly to a planar glass layer and surrounded by mold. One or more redistribution layers may be located above and below the apparatus.