The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Jul. 12, 2023
Applicant:

Zhuhai Access Semiconductor Co., Ltd, Guangdong, CN;

Inventors:

Xianming Chen, Guangdong, CN;

Benxia Huang, Guangdong, CN;

Lei Feng, Guangdong, CN;

Jindong Feng, Guangdong, CN;

Yejie Hong, Guangdong, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 14/68 (2026.01); H10P 14/20 (2026.01); H10P 14/60 (2026.01); H10P 50/00 (2026.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10W 20/083 (2026.01); H10P 14/274 (2026.01); H10P 14/6532 (2026.01); H10P 14/68 (2026.01); H10P 50/71 (2026.01); H10W 20/043 (2026.01); H10W 20/044 (2026.01); H10W 20/054 (2026.01); H10W 20/075 (2026.01);
Abstract

A method for manufacturing a device embedded packaging structure include laminating a first dielectric material on a copper foil to form a first dielectric layer, and forming a first feature pattern in the first dielectric layer to expose the copper foil, etching the exposed copper foil to form a device opening frame and a via post opening frame to obtain a metal frame, applying an adhesive layer on the metal frame, and mounting a device to the adhesive layer in the device opening frame, laminating a second dielectric material to form a second dielectric layer covering the metal frame and filling the device opening frame and the via post opening frame, forming a via post in the via post opening frame, and forming a first wiring layer and a second wiring layer conductively connected by the via post on the upper and lower surfaces of the second dielectric layer.


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