The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Aug. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Lien Huang, Hsinchu County, TW;

Tze-Liang Lee, Hsinchu City, TW;

Jr-Hung Li, Hsinchu County, TW;

Chi-Hao Chang, Taoyuan City, TW;

Hao-Yu Chang, Taipei City, TW;

Pei-Yu Chou, Hsinchu City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6211 (2025.01); H10D 30/024 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01);
Abstract

A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a first recess between the gate spacers, forming a source/drain contact in the first ILD layer, and forming a second interlayer dielectric (ILD) layer to fill in the first recess between the gate spacers and over the source/drain contact.


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