The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Dec. 08, 2023
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Yan Zhang, Westford, MA (US);

Johannes M. Van Meer, Middleton, MA (US);

Kyu-Ha Shim, Andover, MA (US);

Naushad K. Variam, Marblehead, MA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10D 30/01 (2025.01);
U.S. Cl.
CPC ...
H10B 12/05 (2023.02); H10B 12/485 (2023.02); H10D 30/025 (2025.01);
Abstract

Approaches herein provide devices, systems, and methods of transistor patterning using a frontside implant plus epitaxial process to form a graded junction having a high surface doping concentration for a vertical contact transistor bitline. One method may include delivering ions into a front side of a substrate of a transistor to form a graded junction in the substrate, wherein the substrate is maintained at a temperature greater than 100° C. while the ions are delivered into the substrate, and thermally treating the graded junction. The method may further include forming, after the graded junction is thermally treated, an epitaxial layer over the graded junction, forming a plurality of gates in the epitaxial layer, and processing a backside of the substrate to remove the substrate to the graded junction following formation of the plurality of gates.


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