The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2026

Filed:

Aug. 30, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Anna Maria Conti, Milan, IT;

Umberto Maria Meotto, Dietlikon, CH;

Domenico Tuzi, Balsorano, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/48 (2010.01); G11C 16/04 (2006.01); H01L 25/075 (2006.01); H01L 33/20 (2010.01); H01L 33/62 (2010.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.


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