Resistive random access memory (rram) architecture and method

Abstract

Disclosed are a resistive random access memory (RRAM) structure and operating method. The RRAM structure includes RRAM cells arranged in columns and rows with all cells in a column connected between source and bit lines for the column and with all cells in a row connected to a word line for the row. The RRAM structure also includes peripheral circuitry enabling all memory operations to be performed without selective source line biasing. For example, during a reset operation, the following voltage conditions can be applied: a low positive voltage (e.g., of +1.8V) to the word line of the row containing the selected RRAM cell; a low negative voltage (e.g., of −1.8V) to all other word lines; and another low negative voltage (e.g., of −1.6V) to the bit line of the column containing the selected RRAM cell. All source lines and all other bit lines can be discharged to ground.