The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Jan. 19, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Joan Rey Villarba Buot, Escondido, CA (US);

Zhijie Wang, San Diego, CA (US);

Hong Bok We, San Diego, CA (US);

Aniket Patil, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 20/44 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/701 (2026.01); H10W 20/4424 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 72/071 (2026.01); H10W 72/20 (2026.01);
Abstract

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.


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