The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Sep. 23, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei City, CN;

Inventors:

Xiaofei Sun, Hefei City, CN;

Changhao Quan, Hefei City, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 72/50 (2026.01); H10W 74/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 72/5366 (2026.01); H10W 72/865 (2026.01); H10W 72/877 (2026.01); H10W 72/884 (2026.01); H10W 74/00 (2026.01); H10W 90/291 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package includes a first base plate, first semiconductor structure, second base plate and filling layer. The first base plate has a first surface including first and second signal transmission regions. The first semiconductor structure located on the first surface is electrically connected to the first signal transmission region. The second base plate located on the first base plate includes a base and a first interconnection surface. The first interconnection surface is away from the first surface. The first interconnection surface has first and second interconnection regions communicated with each other. The first interconnection region is electrically connected to the second signal transmission region. The filling layer seals the first semiconductor structure, second base plate and first surface. The first interconnection region is not sealed, and the second interconnection region is. There is a preset height between a top surface of the filling layer and the first interconnection region.


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