The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Sep. 06, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Terrence B. Mcdaniel, Boise, ID (US);

Bret K. Street, Meridian, ID (US);

Wei Zhou, Boise, ID (US);

Kyle K. Kirby, Eagle, ID (US);

Amy R. Griffin, Boise, ID (US);

Thiagarajan Raman, Boise, ID (US);

Jaekyu Song, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 72/00 (2026.01); H10W 90/00 (2026.01); H10W 72/50 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 72/0198 (2026.01); H10W 90/00 (2026.01); H10W 72/07552 (2026.01); H10W 72/07553 (2026.01); H10W 72/521 (2026.01); H10W 72/527 (2026.01); H10W 72/531 (2026.01); H10W 72/537 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/752 (2026.01);
Abstract

This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.


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