The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Dec. 21, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Veronica Strong, Hillsboro, OR (US);
Aleksandar Aleksov, Chandler, AZ (US);
Georgios Dogiamis, Chandler, AZ (US);
Telesphor Kamgaing, Chandler, AZ (US);
Neelam Prabhu Gaunkar, Chandler, AZ (US);
Brandon Rawlings, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 70/05 (2026.01); H10W 70/63 (2026.01); H10W 70/66 (2026.01); H10W 72/00 (2026.01); H10W 90/00 (2026.01); H10W 90/22 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/095 (2026.01); H10W 70/635 (2026.01); H10W 90/00 (2026.01); H10W 70/66 (2026.01); H10W 72/823 (2026.01); H10W 90/22 (2026.01);
Abstract
Methods, systems, apparatus, and articles of manufacture are disclosed for integrated circuit package substrates with high aspect ratio through glass vias. An example microelectronic package including a glass substrate including a via, the via including a high aspect ratio. The example microelectronic package further including a seed layer extending substantially evenly along an inner wall of the via.