The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Feb. 13, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Chiang Tsai, Hsinchu City, TW;

Jeng-Ya Yeh, New Taipei City, TW;

Mu-Chi Chiang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H10D 64/23 (2025.01); H10W 20/00 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/42 (2026.01); H10D 64/258 (2025.01); H10W 20/033 (2026.01); H10W 20/056 (2026.01); H10W 20/082 (2026.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a conductive structure. The method includes forming a first dielectric layer over the conductive structure. The method includes forming a conductive via structure that passes through the first dielectric layer. The conductive via structure is over and connected to the conductive structure, the conductive via structure has a first portion and a second portion over the first portion, and a first overall diffusion rate of the second portion in the first dielectric layer is lower than a second overall diffusion rate of the first portion in the first dielectric layer. The method includes forming a second dielectric layer over the conductive via structure and the first dielectric layer. The method includes forming a conductive line that passes through the second dielectric layer.


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