Stacked cmos image sensor and method of manufacturing the same

Abstract

Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor with a high full well capacity (FWC). A first integrated circuit (IC) chip and a second IC chip are stacked with each other. The first IC chip comprises a first semiconductor substrate, and the second IC chip comprises a second semiconductor substrate. A pixel sensor is in and spans the first and second IC chips. The pixel sensor comprises a transfer transistor and a pinned photodiode adjoining the transfer transistor at the first semiconductor substrate, and further comprises a plurality of additional transistors (e.g., a reset transistor, a source-follower transistor, etc.) at the second semiconductor substrate. A bulk of the first semiconductor substrate and a bulk of the second semiconductor substrate are electrically isolated from each other and are configured to be biased with different voltages (e.g., a negative voltage and ground).