The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Jun. 21, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Hsin-Hsien Chen, New Taipei City, TW;

Sheng-Yuan Hsueh, Tainan City, TW;

Kun-Szu Tseng, Tainan City, TW;

Kuo-Hsing Lee, Hsinchu County, TW;

Chih-Kai Kang, Tainan City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/62 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/62 (2025.01); H10D 30/65 (2025.01); H10D 62/116 (2025.01); H10D 64/252 (2025.01); H10D 64/514 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor device includes a substrate. A high voltage transistor is disposed within a high voltage region of the substrate. The high voltage transistor includes a first gate dielectric layer disposed on the substrate. A first gate electrode is disposed on the first gate dielectric layer. A first source/drain doping region and a second source/drain doping region are respectively disposed in the substrate at two sides of the first gate electrode. A first silicide layer covers and contacts the first source/drain doping region and a second silicide layer covers and contacts the second source/drain doping region. A first conductive plate penetrates the first silicide layer and contacts the first source/drain doping region. A second conductive plate penetrates the second silicide layer and contacts the second source/drain doping region.


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