The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Jun. 15, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Ta-Wei Chiu, Changhua County, TW;

Ping-Hung Chiang, Tainan City, TW;

Chia-Ling Wang, Tainan City, TW;

Wei-Lun Huang, Tainan City, TW;

Chia-Wen Lu, Tainan City, TW;

Yueh-Chang Lin, Tainan City, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/27 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10P 50/00 (2026.01);
U.S. Cl.
CPC ...
H10D 64/516 (2025.01); H10D 30/65 (2025.01); H10D 62/116 (2025.01); H10D 64/01 (2025.01); H10P 50/691 (2026.01);
Abstract

A method of manufacturing a semiconductor structure with flush shallow trench isolation and gate oxide, including performing a first etching process to remove a pad oxide layer at one side of a STI and recess the substrate, the first etching process also forms a recess portion not covered by the first etching process and a protruding portion covered by the first etching process on the STI, forming a gate oxide layer on the recessed substrate, performing a second etching process to remove the protruding portion and the pad oxide layer and a first oxide layer on a drain region, performing a third etching process to remove a part of the STI and a second oxide layer, so that a top plane of the STI is flush with the gate oxide layer.


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