The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Apr. 12, 2022
Enabling anneal for reliability improvement and multi-vt with interfacial layer regrowth suppression
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Ruqiang Bao, Niskayuna, NY (US);
Huiming Bu, Glenmont, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 14/20 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/01354 (2026.01); H10D 64/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10P 14/3462 (2026.01);
Abstract
A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.