The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2026

Filed:

Aug. 04, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yen Yu Chen, Pingtung City, TW;

Ming-Yen Tsai, Changhua County, TW;

Wen-Hsing Hsieh, Hsinchu City, TW;

Ying-Han Chiou, Tainan City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10B 10/125 (2023.02); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6735 (2025.01); H10D 64/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01);
Abstract

A method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. The dielectric structure divides the metal gate into two sections.


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